1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
2. Discussion of the Related Art
A nonvolatile memory device may be a floating gate type device or a charge trap type device. A floating gate nonvolatile memory device is an example of a flash memory device while a charge trap nonvolatile memory device is an example of a silicon-oxide-nitride-oxide-silicon, or SONOS, memory device. The charge-trap device has a MOS transistor structure in which a multilevel charge storage layer is used as a gate insulating layer. The charge-trap device is thereby enabled to have writing and erasing voltages lower than those of the floating-gate device. Therefore, the charge-trap device can be operated at lower power, with a smaller area for a peripheral circuit, e.g., a voltage pump. The charge-trap device can also be operated with higher reliability due to its use of a spatially isolated insulating layer for storing charges.
FIGS. 1A and 1B illustrate a related art nonvolatile memory device having a multilevel charge storage layer.
Referring to FIGS. 1A and 1B, a device isolation film 12 is formed in a semiconductor substrate 10 to define a plurality of parallel active regions. Word lines 16 are formed above the active regions by interposing a charge storage layer 14. The word lines 16 pass above the device isolation film 12, that is, above the surface of the semiconductor substrate 10, to cross over the active regions. Source/drain regions 18s and 18d are respectively formed in the active regions at both sides of the word lines 16. The source region 18s is formed between two adjacent word lines 16. Each source region 18s is connected with another source regions 18s of other active regions where there is no formation of the device isolation film 12. Common source lines, to which a plurality of source regions are connected, are formed between and in parallel with the word lines 16. By contrast, each drain region 18d is isolated between formations of the device isolation film 12, such that the formation of each drain region is restricted to an active region. A sidewall insulating film 20 forms spacers at sidewalls of the word lines 16.
The word lines may be patterned by a photolithographic process, and after their formation, the common source lines are formed by etching the device isolation film using the word lines as an etching mask. Then, impurity ions are implanted. Therefore, any desired reduction in the width of each word line and each source line is inherently limited. The limitations restrict attempts to increase the integration of a nonvolatile memory device by reducing the unit cell size.